A logic circuit is a circuit designed to perform a particular logical function based on the concepts of "and," "either-or," "neither-nor," etc. Normally, these circuits operate between two discreet voltage levels, i.e., high and low logic levels, and are described as binary logic circuits. Binary logic circuits are the basic building blocks of data processing systems and almost any electronic computing device. Binary logic circuits are extensively used in computers to carry out instructions and arithmetic processes. Any logical procedure may be effected by using a suitable combination of these basic gates. Because of their low power dissipation, complementary metal-oxide semiconductor (CMOS) field-effect transistors (FETs) are often used to construct such logic circuits.
Logic circuits are often cascaded in a plurality of connected stages. As a result, clock pulses are applied to the elements of a logic circuit to effect logical operations, i. e., drive the logical circuit. Referring now to FIG. 1, there is illustrated a typical logic circuit 100, which may implement any logical function, having Data In inputs and a Data Out output. A Clock signal is input to the logic circuit 100 in order to drive the Data In inputs through the logic circuit 100 and effect the associated logical function implemented in the logic circuit 100 upon the inputs to arrive at the logical solution, which is output as Data Out. The Clock signal also serves to prepare, or precharge, the logic circuit 100 so that it is ready for the next series of Data In inputs subsequent to outputting the previous Data Out.
Referring now to FIG. 2, there is illustrated, in block diagram form, a plurality of dynamic logic circuits 200, 202 and 204 coupled in some type of combination, such as the shown series combination (sometimes referred to "domino" circuitry). Each of the dynamic logic circuits 200, 202 and 204 require a clock signal for operation. The dynamic logic circuit 200 performs a logic function on the input(s) DataIn and outputs DataOut1. The dynamic logic circuit 202 performs a logic function on the signal DataOut1 (and perhaps one or more additional input signals identified as DataIn1) and outputs DataOut2. The dynamic logic circuit 204 performs a logic function on the signal DataOut2 (and perhaps one or more additional input signals identified as DataIn2) and outputs DataOut3.
In some applications, it is desirable to have both the output signal and the complement of the output signal of a preceding stage of the cascaded dynamic logic circuits (for example, having the complement of DataOut1 input to the dynamic logic circuit 202 or the complement of DataOut2 input to the dynamic logic circuit 204) input to a particular dynamic logic circuit. In other words, some dynamic logic circuits require a dual-rail signal as an input. When both the output signal and its complement are needed for input to the next stage, the complement is typically generated by simply inverting the output by utilizing an inverter. However, there is a problem with inverting the output signal for input to the next successive stage in typical domino dynamic logic circuits.
Referring now to FIG. 3, there is illustrated a typical "domino" dynamic logic circuit 300, which in this example is a non-inverting buffer. An input signal to be evaluated is received at the gate electrode of an N-channel FET ("NFET") 312, while a P-channel FET ("PFET") 311 and an NFET 313 both receive a clock input at their gate electrodes (please note, NFETs are designated with the letter N in the FIGURES while PFETs are designated with the letter P). Referring to FIGS. 3 and 4 in combination, an important limitation of this type of dynamic logic circuit may be seen. Note that during the precharge phase, the clock input precharges a node 316 to a high level, and then during the evaluate phase, the dynamic logic circuit 300 evaluates the input signal received by the NFET 312 and outputs the evaluation through the optional half latch comprising a PFET 314 and an inverter 315.
The input signal may change in either direction during the first part of the precharge phase, and may change from a low level to a high level at the end of the precharge phase during the evaluate phase and still allow the logic circuit to output the correct output signal. However, during the evaluate phase, a change of the input signal from a high level to a low level will result in an output that may not be the correct output signal. The reason for this is that a changing input signal can cause the dynamic precharge of the node 316 to lose its high level precharge condition and not be able to recover this high level if the logical input conditions are such that this is the desired logical condition. In other words, if during the evaluate phase the input signal transitions from a high level to a low level, it is possible that the output of the dynamic logic circuit 300 may still be a high level even though this is not what is expected if the input signal is now at a low level.
This problem is more specifically stated as follows: during the evaluation phase, input signals may change if the change is from a low to a high, but may not change from a high to a low. This condition can occur when a "static signal" is fed into a dynamic logic circuit (i.e., the static signal is converted to dynamic timing). A typical "static signal" can be expected to change state almost anywhere within a timing cycle.
Accordingly, in a typical cascaded logic circuit as illustrated in FIG. 2, where the complement of the output signal of one of the dynamic logic circuits is needed as an input to another dynamic logic circuit, simply inverting the output signal to generate the complement may cause the dynamic logic circuit to falsely switch.
There exist two possible solutions to this problem, however, each of these solutions has its own disadvantages and may create additional problems. One possible solution is to delay the clock signal of the receiving stage in order to guarantee that the arrival of the clock signal is later than the data. However, delaying the clock requires the addition of clock skew generating circuits used to create the clock delay. Moreover, the addition of delay injects additional timing constraints on the logic circuit and overall data processing system.
The other possible solution involves the addition of duplicate circuitry to generate a complement signal when the complement is required to perform logic. This solution is illustrated in FIG. 5 using the cascaded dynamic logic circuits 200, 202 and 204 of FIG. 2. The dynamic logic circuit 204 includes a logic function that requires the complement of the output signal (DataOut2) from the dynamic logic circuit 202. To generate the complement of the DataOut2 signal, additional dynamic logic circuits 500 and 502 are required to generate the complement using the complements of the DataIn signal(s) and the DataOut1 signal(s). The major problem with this type of solution is the need for additional duplicate circuitry that may include a significant number of transistors and reduce available space on an integrated circuit.
Accordingly, there exists a need for a logic circuit that eliminates false switching in domino dynamic logic circuits caused by inadvertent voltage transitions on an input signal. Further, there is needed a logic circuit that allows for the generation of a complement signal from an output signal of a dynamic logic circuit using simple inversion means, and further allows for the use of the generated complement signal as an input to a dynamic logic circuit by reducing the potential for false switching caused by the complement signal. In addition, there is needed a logic circuit that performs the above functions without the need for clock skew or additional duplicate circuitry.